The present invention is related to systems and methods for performing data processing, and more specifically to systems and methods for scheduling processes in a data processing circuit.
Data processing circuits often include a data detector circuit and a data decoder circuit. In some cases many passes are made through both the data detector circuit and the data decoder circuit in an attempt to recover originally written data. Each pass through both data detector circuit and the data decoder circuit may include a number of iterations through the data decoder circuit. In some cases, a default processing through the data decoder and data detector circuits may not yield a correct result.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data processing.